1. Field of the Invention
The present invention relates to a semiconductor device fabrication method, and in particular to an improved semiconductor device fabrication method capable of improving an insulation characteristic between neighboring electrodes and a storage capacity of a semiconductor device.
2. Description of the Conventional Art
As is well known to those who skilled in the art, a DRAM is a kind of a semiconductor memory device consisting of a cell selection transistor and a capacitor as a basic cell. The gate of the cell selection transistor is connected to a word line, and the drain thereof is connected to a bit line, and the source thereof is connected to the capacitor having one end connected to the ground. Here, a data storing operation is executed in accordance with an electric charge stored in the capacitor. Recently, 256 MDRAM had been introduced in the industry, and a device having more intensive memory capacity has been widely developed.
The conventional art has been focused upon developing capacitance which is essential in storing data. It was attempted to simply change the construction of a dielectric film or to provide a certain groove on a substrate in the planarized interconnection technology so as to use the groove as a capacitor, or to develop a three dimensional construction capable of depositing a conductive layer on a substrate. Capacitors having various constructions are currently being developed in the industry.
FIG. 1 shows a three dimensional stack type capacitor, which is directed to depositing a conductive layer on the substrate. That is, this capacitor is directed to forming a groove on the substrate, so that it is easier to fabricate the stack type capacitor compared with a trench type capacitor, and it is possible to provide greater capacitance.
In more detail, the stack type capacitor, as shown in FIG. 1, is connected to a source/drain region of the transistor, and the bit lines BL cross the word lines WL.
FIG. 2 shows a conventional stack type capacitor, which includes a field oxide film 20 formed to define an active region and a nonactive region, a gate insulation film and gate electrode 4 formed by depositing and patterning an insulation material and a conductive material on the front surface of a certain construction obtained by forming the field oxide film 20 in order, a source/drain region 2 formed by providing foreign matters on the semiconductor substrate after masking the gate electrode 4, an oxide film 5 formed so as to insulate between the gate electrode 4 and the upper construction thereof, a storage electrode 6 formed by depositing and patterning a conductive material through a contact hole so that the storage electrode 6 is not connected to the source/drain region, a dielectric film formed by depositing a dielectric material on the storage electrode 6, a plate electrode 7 formed by depositing a conductive material on the dielectric film, a contact oxide film 8 formed on the plate electrode 7, a bit line 9 formed by depositing and patterning a conductive material on the contact oxide film 8, an insulation film 10 and a metal wiring layer 12 formed by depositing an insulation material so as to insulate between a bit line and the metal wiring layer 12 after forming the bit line 9.
Here, the bit line 9 is formed at the bottom of a slanted contact hole having an upper portion wider than the lower portion. As shown in FIG. 2, there is a problem in that the insulation film that isolates the gate electrode and the bit line at a portion "A" becomes thin, and when the device has a narrow surface due to the error alignments of the contact mask and the intensity, an electrical short may take place between the gate electrode and the bit line, so that the reliability of the products is decreased.